1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the present invention relates to a power-up detection circuit for use in a semiconductor device.
2. Discussion of Related Art
Generally, in order to guarantee stable operation of a semiconductor device, the semiconductor device has to operate within a predetermined operational power range. To this end, the semiconductor device includes a power-up detection circuit for detecting the level of a power supply voltage when power is supplied. The power-up detection circuit generates a control signal to initialize internal circuits of the semiconductor device when the power supply voltage serves as an operational voltage, and generates a control signal, which controls the internal circuits of the semiconductor device to enter a power-off mode, when the power supply voltage exceeds the operational voltage.
FIG. 1 is a circuit diagram of a conventional power-up detection circuit. Referring to FIG. 1, the power-up detection circuit 10 includes resistors R1, R2, a PMOS transistor P1, a NMOS transistor N1, and an inverter 11. The operation of the power-up detection circuit 10 is described below.
A voltage VDD is divided by the resistors R1, R2. A signal D1, having a voltage level divided in a node A1, is thus output. The NMOS transistor N1 is turned on or off according to the voltage level of a signal D1. A voltage level of a signal D2 generated from a node A2 is also changed depending upon the operation of the NMOS transistor N1. For example, when the voltage VDD increases, the voltage level of the signal D1 increases in proportion to the voltage VDD. If the voltage VDD becomes a voltage level to which the voltage level of the signal D1 is set, the NMOS transistor N1 is turned on. As a result, the voltage level of the signal D2 abruptly decreases. The inverter 11 senses such an abrupt decrease in the voltage level, and thus enables a detection signal PWRUP.
Since the current driving ability of the PMOS transistor P1 and the NMOS transistor N1 can be changed according to process, voltage and temperature (hereinafter, referred to as “PVT”), however, the power-up detection circuit 10 may operate erroneously. In other words, even when the voltage VDD exceeds a stable operational voltage, the power-up detection circuit 10 can detect that the voltage VDD is a stable operational voltage. Additionally, even when the voltage VDD falls within a stable operational voltage, the power-up detection circuit 10 can detect that the voltage VDD exceeds a stable operational voltage.
The operation of the power-up detection circuit 10 depending upon variation in PVT will be described in more detail with reference to FIG. 2. The voltage level of the signal D1 has nothing to do with variation in PVT. This is because resistance values of the resistors R1, R2 are likely to vary in proportion to variation in PVT. That is, if a resistance value of the resistor R1 increases, a resistance value of the resistor R2 increases in proportion to the resistance value of the resistor R1. Therefore, the voltage level of the signal D1 generated from the node D1 increases proportionally when the voltage VDD increases regardless of variation in PVT, as shown in FIG. 2.
The voltage level of the signal D2 generated from the node A2, however, varies in various manners depending upon variation in PVT. In other words, the speeds of the NMOS transistor N1 and the PMOS transistor P1, which respond to voltages input to their gates, vary depending upon variation in PVT. In FIG. 2, “TT” indicates a waveform of the signal D2 when the response speeds of the NMOS transistor N1 and the PMOS transistor P1 are typical and a temperature thereof is 25° C. “FF” indicates a waveform of the signal D2 when the response speeds of the NMOS transistor N1 and the PMOS transistor P1 are the fastest and a temperature thereof is 125° C. Further, “SS” indicates a waveform of the signal D2 when the response speeds of the NMOS transistor N1 and the PMOS transistor P1 are the slowest and a temperature thereof is −10° C. “SF” indicates a waveform of the signal D2 when the response speed of the NMOS transistor N1 is the slowest and the response speed of the PMOS transistor P1 is the fastest, and a temperature thereof is 125° C. Moreover, “FS” indicates a waveform of the signal D2 when the response speed of the NMOS transistor N1 is the fastest and the response speed of the PMOS transistor P1 is the slowest, and a temperature thereof is −10° C.
As shown in FIG. 2, if the voltage VDD increases, the voltage level of the signal D1 also increases proportionally. The voltage level of the signal D2 increases in proportion to the voltage VDD until the NMOS transistor N1 is turned on, but abruptly transitions to a low level at a time where the NMOS transistor N1 is turned on. It can be seen that, among the waveforms “FF”, “SS”, “TT”, “SF” and “FS”, the waveform “FS” shifts to a low level fastest, and the waveform “SF” transits to a low level slowest. Furthermore, a time where the NMOS transistor N1 is turned on in the waveform “FS” is when the voltage VDD becomes a voltage Vd1, and a time where the NMOS transistor N1 is turned on in the waveform “SF” is when the voltage VDD becomes a voltage Vd2. As a result, a target voltage value that must be detected by the power-up detection circuit 10 can vary from Vd1 to Vd2 depending upon variation in PVT. Moreover, since the target voltage value of the power-up detection circuit 10 varies greatly, there is an increasing possibility that the power-up detection circuit 10 may operate erroneously. This problem is even more likely in the case of a low power semiconductor device having a low operating voltage. For example, in a semiconductor device having an operating voltage of 1.5V, if a target detecting value of the power-up detection circuit 10 is changed to 2V due to variation in PVT, the power-up detection circuit 10 controls the semiconductor device to enter a power-off mode if the voltage VDD becomes lower than 2V.
As such, the semiconductor device cannot operate in a stable way due to such malfunction of the power-up detection circuit 10. As described above, in the conventional power-up detection circuit, a target detecting voltage can vary due to variation in PVT. Accordingly, there is a problem in that stable operation of a semiconductor device cannot be guaranteed.